The electronics industry is facing serious challenges because of the increased demand on functionality and strong pressures on both time-to-market and cost requirements. The complexity designers have to deal with creates design quality problems that force serious delays in product introductions and even product recalls. There is a need for methodologies and tools that can drastically reduce design errors and costs. Electronic System Level (ESL) tools attempt to fulfill this need by increasing the abstraction and modularity by which designs can be specified. However, simply because these design styles are introduced, this does not automatically imply an acceptable level of accuracy and efficiency required for widespread adoption and eventual success. This thesis introduces a design flow which improves abstraction and modularity while remaining highly accurate and efficient. Specifically this work explores a Platform-Based Design approach to model architectural services.

Platform-Based Design is a methodology in which purely functional descriptions of a system are top-down assigned (or mapped) to architecture services which have their models for capabilities and costs exported from the bottom up. Architecture services are a set of library elements characterized by their capabilities (what functionality they support) and costs (execution time, power, etc). These libraries of components "parametrize" the set of architecture services that can be chosen by the designer to implement functionality and limit the design space thus favoring design re-use. The design process then proceeds toward implementation by binding functionality to architectures composed of elements from the library. The components that form a platform instance are selected by evaluating their capability of supporting the mapped functionality within the design constraints and by optimizing objective functions.

The design flow proposed in this thesis specifically focuses on how to create architecture service models of programmable platforms (FPGAs for example). These architecture service models are created at the transaction level, are preemptable, and export their abilities to the mapping process. An architecture service library is described for Xilinx's Virtex II Pro FPGA. If this library is used, a method exists to extract the architecture topology to program an FPGA device directly, thus avoiding error prone manual techniques. As a consequence of this programmable platform modeling style, the models can be annotated directly with characterization data from a concurrent characterization process to be described.

Finally, in order to support various levels of abstraction in these architecture service models, a refinement verification flow will be discussed as well. Three styles will be proposed each with their own emphasis (event based, interface based, compositional component based). They are each deployed depending on the designer's needs and the environment in which the architecture is developed. These needs include changing the topology of the architecture model, modifying the operation of the architecture service, and the exploring the tradeoffs between how one expresses the services themselves and the simulation infrastructure which schedules the use of those services.

To provide a proof of concept of these techniques, several design scenarios are explored. These scenarios include Motion-JPEG encoding, an H.264 deblocking filter, an SPI-5 networking protocol, and a communication structure of a highly concurrent system architecture (FLEET). The results show that not only is the proposed design flow more accurate and modular than other approaches but also that it prevents the selection of more poorly performing designs or the selection of incorrectly functioning designs through its emphasis on the preservation of fidelity.