Semi-custom design of high-performance VLSI processors has been demonstrated by the Berkeley VLSI-PLM chip using Mentor Graphics IDEA station, Cell station tools and NCR tools. To support semi-custom design using Berkeley VLSI tools such as LagerIV, we have developed a set of cells. These cells are designed with the goal of designing a high-performance VLSI Parallel Prolog Processor. They can be used in other designs such as DSP chips. Some of these cells complement those in LagerIV's DPP cell library. Others provide an area efficient replacement for the DPP cells.
Title
Area Efficient Cells for LagerIV's DPP Library
Published
1989-08-01
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
CSD-89-531
Type
Text
Extent
40 p
Archive
The Engineering Library
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