High-speed analog-to-digital converters (ADCs) are key enabling blocks for emerging wideband applications in communication, high-end instrumentation, and medical imaging. Larger signaling bandwidths improves system performance, and necessitates high-speed ADCs for accurate digitization. As an example, current state-of-the-art oscilloscopes have an acquisition bandwidth exceeding 60GHz with effective sample rates greater than 100GS/s. This places significant difficulty in the design of sample-and-hold (S/H) and analog-to-digital conversion circuitry that can operate at such high speeds while providing moderate resolution. As a result, the front-end of these systems are often complex, multi-chip solutions that are fabricated in expensive processes such as indium-phosphide (InP). With the increased demand for battery-operable, low-power systems it is desirable to have these high-performance signal acquisition systems in a fully-integrated CMOS implementation in order to harness the power of scaling as dictated by Moore's law. To achieve this, several advancements on current data conversion techniques need to be made. In this thesis, we explore the design and optimization of a frequency-interleaved ADC (FI-ADC) as an alternative to conventional high-speed ADC architectures, which are often heavily time-interleaved. Due to the large interleaving factor and timing sensitivity, the conventional architectures are often very power hungry and offer typical resolutions of 4 bits or less. FI-ADCs, in which the input signal is divided into various frequency bands which are independently digitized and digitally recombined, show less susceptibility to jitter, the primary bottleneck in high-speed ADCs. System simulations have shown a potential improvement in SNR performance for a frequency-interleaved ADC versus a direct sampling, time-interleaved architecture. The focus of this thesis is to provide a fundamental understanding of the operation of the FI-ADC and investigate the similarities and differences to the conventional time-interleaved ADC in respect to design complexity, design challenges and overall performance.




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