This report presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.
Title
A Physical Poly-Silicon Thin Film Transistor (TFT) Model for Circuit Simulation
Published
1993-11-01
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
ERL-93-82
Type
Text
Extent
62 p
Archive
The Engineering Library
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