In today's systems, the interconnection network which enables communication among multiple discrete processing cores frequently becomes the performance bottleneck. Our project seeks to improve upon this interconnect with the goal of better overall system performance. Specifically, our project focuses on creating a high-radix router to reduce network latency. This report describes our industry analysis, recommended business strategies, and technical work in conducting a design space exploration for high-radix routers with up to 64 ports. We set up a Synopsys-based tool flow and ran multiple designs through place-and-route to collect statistics for different configurations. We also replaced a flip-flop based register file with SRAM's to achieve around 15% area improvement with about 10% power, while having minimal impact upon critical path.