This report discusses the design and simulation results of an ultra low power receiver front end circuit for the ISM band(2.4GHz). The design has been done using a 65nm CMOS process. The direct conversion receiver architecture employs synchronous detection using a local oscillator whose frequency is same as the carrier frequency of the signal. As a result, the circuit complexity is significantly reduced, enabling integration with the baseband circuitry. Using simultaneous Inphase(I) and Quadrature(Q) mixing, the image problem is eliminated. This project investigates both active and passive downcoversion techniques. Besides, driver circuits have also been designed to amplify and buffer the VCO output to drive the Local Oscillator(LO) ports of the mixer. The receiver based on the active mixer has a simulated noise figure of 4.8dB, IIP3 of -19dBm and a power consumption of 1.95mW including the LO drivers. The receiver based on the passive mixer has a simulated noise figure of 4.8dB, IIP3 of -15dBm and a power consumption of 1.92mW, with the mixers and LNA alone consuming 1.6mW. The active mixer is based on a single balanced topology whereas the passive mixer is based on a fully differential Transimpedance Amplifier(TIA) to convert the mixer current to voltage output. A CMOS Transimpedance amplifier along with Common Mode Feedback(CMFB) circuit have also been designed for implementing the passive mixer. The LO driver-buffer stage comprises of an amplifier and series of invertors for achieving the requisite fanout to drive the LO input ports of the mixer. All circuits have been implemented at transistor level and have realistic passives with a quality factor of 10 for inductors and 50 for capacitors. The maximum supply voltage is 1V. This power constrained design is a tradeoff between noise, linearity and power dissipation.