In 1995, the FCC allocated the spectrum from 59GHz to 64GHz as an unlicensed band, and shortly thereafter, extended this unlicensed band to 57-64GHz, thus providing 7GHz of unlicensed spectrum for general purpose use. Similarly, regulatory bodies across the globe have also set aside multi-GHz blocks of spectrum at 60GHz for unlicensed use. The presence of a true multi-GHz worldwide band has sparked immense interest in developing high-throughput 60GHz communications systems. Furthermore, the demonstration of CMOS mm-wave circuitry in recent years has made feasible the possibility of a highly integrated, all-CMOS 60GHz transceiver. However, the design of such a system is made quite difficult by several factors: first, the 60GHz indoor channel has increased transmission loss due to both the increased free-space loss and the poor transmissivity of common building materials. As a result, systems employing omnidirectional antennae cannot achieve Gbps rates, and more complex systems employing adaptive beamforming must be architected. Secondly, the limited performance of CMOS mm-wave components requires new approaches to system and architecture design, as the high level of system performance must be maintained with relatively low quality mm-wave circuits. The work presented in this dissertation focuses on the analysis, specification, and design of a baseband system and architecture for 1Gbps, 60GHz wireless receiver. System exploration is conducted in order to find a suitable architecture for a high-performance system composed of limited-performance CMOS mm-wave circuitry. A mixed-signal baseband receiver design is proposed in order to minimize the overall power dissipation and implementation complexity. The proposed system performs much of the signal processing related to the task of synchronization in the analog domain, so that the signal is properly conditioned prior to sampling and quantization. This approach reduces the resolution requirements of the high-speed analog-to-digital converters (ADCs), dramatically reducing system power consumption. The proposed architecture was designed and fabricated in a 90nm standard digital CMOS process. The design consists of a mixed-signal carrier phase rotator block with 500Ms/s DDFS DAC, a 16-tap mixed-signal complex decision-feedback equalizer running at 1Gs/s, and two 2Gs/s, 4-bit flash ADCs. This analog front-end achieves a peak SNDR of 24.8dB at the full Nyquist rate, has linearity exceeding 38dB, and dynamic range greater than 31dB. Overall chip power consumption is 55mW.




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