Simulation continues to be a major tool in the design of digital circuits. With increases in design sizes and the relative simulation times, the need for better simulation performance, covering both software techniques and hardware acceleration methods. This report combines both ideas. On the software side, the concept is presented for using logic synthesis techniques to produce better implementations of a circuit for functional simulation. From a hardware perspective, this concept is investigated using a simulator running on a massively parallel SIMD computer. Synthesis tools are used to modify the functional description of a circuit to increase the parallelism and shorten the expected simulation time while mapping the description for execution on the parallel architecture.
Title
Logic Synthesis and Massively Parallel Computers: Tools for Speeding-Up Logic Simulation
Published
1993-01-01
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
ERL-93-16
Type
Text
Extent
54 p
Archive
The Engineering Library
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