PDF

Description

This document describes the memory system architecture of the SPUR workstation. SPUR is a bus-based multiprocessor, with caches to reduce each processor's bandwidth requirement. A hardware cache coherency protocol maintains a consistent image of memory across all the caches. A novel address translation scheme eliminates the need for translation buffers.

This document is intended as a reference for system and diagnostic programmers. It describes the cache coherency protocol, address translation algorithm, and exception handling mechanisms in detail.

Details

Files

Statistics

from
to
Export
Download Full History