Minimum as well as maximum circuit delays play vital roles in high performance systems. In this paper, we analyze existing and new minimum delay models and show that these models are special cases of a general circuit delay model introduced in [LBSV92a] which also unifies all maximum delay models. Then, we provide algorithms to compute exactly various minimum circuit delays with arbitrary gate delay models under the same framework. Thus, all minimum and maximum circuit delay models are u unified and their corresponding delays can be computed exactly. Further, we consider the interactions of various minimum and maximum delays with clock frequencies of circuits. Finally, we provide experimental results on ISCAS benchmarks.
Title
Exact Minimum Delay Computation and Clock Frequencies
Published
1993-01-01
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
ERL-93-40
Type
Text
Extent
18 p
Archive
The Engineering Library
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