There are many benefits in the use of additive synthesis for sound production in computer music applications. The challenge of the technique lies in its voracious appetite for separately controllable sinusoidal partials.

This paper summarizes our work developing a real-time additive synthesis engine supporting hundreds of simultaneous partials. It is the implementation for the T0 vector microprocessor. The goal was to provide significantly more real-time partials than were available using conventional general-purpose hardware architectures. The major features of T0 that drive the design is the vector ISA and the use of fixed-point arithmetic. The explicit parallelism of the vector ISA led us to use parallel recursive oscillators. The 16b fixed-point arithmetic required adapting the recursive oscillators to provide additional accuracy. The modified oscillator is a two-pole filter that maintains frequency precision at a cost of one additional operation per filter sample. The new filter's error properties are expressly imperfect, explicitly matched to use in the context of digital audio rather than general-purpose applications. We briefly describe the controlling synthesizer software, the control structure for feeding the oscillators, fast initialization (needed for short additive synthesis windows), and applicability to related architectures. We present algorithm performance analysis and measurements of the implementation, focusing on how chip features affected algorithm design choices. The technique achieves 608 simultaneous real-time partials (at 44.1KHz) with only a 40MHz clock performing 8 operations per cycle (peak), or about 1.5 cycles per partial per sample.




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