In this paper, we present a systematic method of implementing a VLSI parallel adder. First, we define a family of adders, based on a modular design. Our design uses three types of component cells, which we implement in static CMOS. We then formulate the adder design as a dynamic programming problem, optimizing with respect to time. As a result, we have found the fastest 32-bit CMOS adder in our design family.
Title
Time-Optimal Design of a CMOS Adder
Published
1985-08-09
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
CSD-86-252
Type
Text
Extent
15 p
Archive
The Engineering Library
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