Game, multimedia, consumer and control applications today often demand high performance computing platforms that are able to deliver real-time services while satisfying tight power constraints. Multi-core architectures, supported by on-chip networks, are emerging as scalable solutions to fulfill these requirements. However, the increasing number of concurrent applications running on these platforms and the time-varying nature of the communication requirements give rise to communication delays that are difficult to predict.
We propose a simple and flexible instrumentation of the on-chip network that provides services to the application software for establishing end-to-end communication flows with timing guarantees. We provide a detailed analysis of the delay in a NoC using worm-hole flow control and an algorithm that, given the state of the NoC and a request to route a new real-time flow, establishes a suitable path for the route, if one exists, or rejects the request. We implemented the new protocol in a cycle-accurate simulator to validate the accuracy of the models and the correctness of the path establishment algorithm.
On-time Network On-Chip: Analysis and Architecture
Researchers may make free and open use of the UC Berkeley Library’s digitized public domain materials. However, some materials in our online collections may be protected by U.S. copyright law (Title 17, U.S.C.). Use or reproduction of materials protected by copyright beyond that allowed by fair use (Title 17, U.S.C. § 107) requires permission from the copyright owners. The use or reproduction of some materials may also be restricted by terms of University of California gift or purchase agreements, privacy and publicity rights, or trademark law. Responsibility for determining rights status and permissibility of any use or reproduction rests exclusively with the researcher. To learn more or make inquiries, please see our permissions policies (https://www.lib.berkeley.edu/about/permissions-policies).