The silicon-based microelectronics industry has been growing rapidly for the past four decades following Moore's law of scaling. However, fundamental physical limits have heralded the end of conventional linear scaling of transistor dimensions, and a new era of MOSFET scaling constrained by power dissipation and process-induced variations is already here. Fundamental changes in device architecture may be necessary to continue scaling trends with thin-body MOSFETs such as UTB-FETs and FinFETs emerging as leading contenders. This dissertation has addressed many of the key scaling issues involved in the design and performance optimization of thin-body MOSFETs, and highlights applications that take advantage of these projected benefits. Given the difficulties in shrinking transistor dimensions, application-specific device optimization becomes critical for maximizing the benefits in transitioning to these new transistor designs. In this work, the device optimization methodology has been detailed to optimize thin-body FET performance taking into account circuit performance implications such as power, speed and robustness to process-induced variations through the use of device simulation and mathematical modeling to better understand the degree of performance enhancement that can be provided by these new device structures. Back-gated thin-body MOSFETs (BG-FETs) with the capability of dynamic VTH control have great promise in controlling power dissipation as well as in compensating for process-induced variations. The gate delay versus energy consumption tradeoffs study shows that adaptive VTH control in BG-FETs makes them span a wider range in energy-delay space over FinFETs. To further refine the design of BG-FETS, a back-gate bias dependent scale length has been derived and shows that reverse-back gate biasing can be used to extend the scalability of the BG-FET. Designing large SRAM arrays is getting harder due to lowered cell stability with technology scaling and increased degree of process-induced variations. FinFET-based SRAM designs exhibit improved cell stability and can help continue SRAM scaling into sub-45nm technology nodes. A new FinFET-based SRAM cell design with dynamic feedback is shown to provide significant improvement in cell static noise margin, without area or leakage penalty. Process modules required to integrate these SRAM designs such as resist planarization, etch-back and selective gate separation have been demonstrated.




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