The performance of modern IC devices is often determined by, among other factors, the value of the parasitic gate to source/drain overlap capacitance. It is therefore desirable to determine the overlap capacitance in order to have a better model of the device, so that one can bin the ICs during production based upon speed and performance. In high volume production, measurement results of early runs can be used to improve the process. Since capacitance measurements are tedious and time consuming, they are not practical to perform during production. On the other hand, DC current measurements are performed as routine electrical tests. The objective of this paper is to introduce a technique that infers the gate-to-drain/source overlap capacitance of submicron devices by simple DC measurements. The inference is based on the asymmetry of the device, typically caused by angled ion implantation. For certain values of tox, implantation angle, dopant concentration, and drive-in time, a linear model can be built experimentally to determine the gate-to-drain overlap capacitance (Cgd) and gate-to-source overlap capacitance (Cgs) based strictly on DC measurements; the DC measurements would be the measurements of the two saturation currents of the device interchanging its source and drain. In an IC production facility, a model can be built from experimental data obtained from early runs. Then routine DC measurements will determine the Cgs and Cgd throughout production.




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