This paper provides a comparative study of the proposed global clock distribution methods for high-speed digital integrated circuits. Both non-networked and distributed schemes such as travelling and standing wave clock distributions have been reviewed. Performance metrics are described and qualitatively discussed and non-networked approaches were simulated in a low-power 65nm CMOS process.
Title
High-Frequency Clock Distribution Methods in Digital Integrated Circuits
Published
2017-06-06
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2017-116
Type
Text
Extent
7 p
Archive
The Engineering Library
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