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Abstract In the wake of the growing amount of data being processed every day around the world, and especially in data centers, we want to find a way to handle this increasing demand. An obvious way to solve this issue is to be able to send those data faster and faster. This is the goal of this project which aims at building a modern High-Speed Link that can process data at a rate of 25Gb/s. Basically, we want to send data from a transmitter to a receiver. If we consider the straightforward solution of data transiting into a simple wire between those two blocks, we might encounter some problems. Indeed, at those speed, we have to cope with bandwidth limitation, noise, interference that will deteriorate the original signal. So, we want to build specific tools at the receiver side in order to recover this initial signal and get a clean received signal. The current architecture for those links are made of a serializer, a PLL, a transmitter, a channel, a receiver, a clock data recovery and a desrializer. The first step is to send data from one specific chip. We will receive data coming from different part of the chip at the same time. However, all those data will travel through one channel. So, we need to serialize those incoming data packets. The serializer realizes this operation. The PLL will be responsible to generate the clock that set at which rate the data is sent into the channel. The data will be sent by the transmitter and will travel through the channel. The receiver will receive it. Inside this receiver, a specific architecture, which will be the main focus of this paper, will try to recover the original signal that has been affected by the link. The data recovery block will try to synchronize its clock to the original one so that it can sample the signal when it is the cleanest possible. As stated before, this paper focus on the correcting architecture at the receiver. The whole design flow of this bloc will be described. The first part is to understand how the channel affect the quality of the signal. Thanks to different matlab simulations, we were able to characterize the different modules required for this integrated circuit in order to balance the effect of the channel. Then, this paper will introduce the actual design of this circuit with Cadence Virtuoso. The last part consist of the layout of this architecture. The final product (comprising the two other papers associated to this project) is a fully operational layout of the receiving block that can treat data at a rate of 25Gb/s.

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