To fuel an increasing need for parallel performance, system designers have resulted to using multiple sockets to provide more hardware parallelism. These multi-socket systems are harder to program for scalable performance than their single socket counterparts because of Non-Uniform Memory Access (NUMA). It is costly to increase the inter-socket bandwidth because of pin count and power restrictions imposed by the electrical interconnect. Silicon photonics provides an opportunity to fix this because it offers significant energy efficiency and bandwidth density advantages, especially off chip. Using silicon photonics, the interconnect both on chip and off chip can be over-provisioned to provide full bandwidth between all sockets to return some of the programmability.

If the penalties to making a multi-socket system are negated by the use of silicon photonics, there is incentive to break up single socket designs into multiple smaller sockets. Smaller dies should increase yield and thus dramatically reduce cost. With smaller dies, the manufacturer is also given finer granularity when binning chips to deal with process variation. A single reusable design could build a range of systems and should reap further cost reduction from increased yield. In this paper, we present this scalable and coherent multi-socket design along with discussing the tradeoffs facing an architect when incorporating silicon photonics technology.





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