The IBM 360/85, possibly the first commercially available CPU with a cache memory, used a cache with a sector design, by which the cache consisted of sectors (with address tags) and subsectors (or blocks, with valid bits). It rapidly became clear that superior performance could be obtained with the now familiar set-associative cache design. Because of changes in technology, the time has come to revisit the design of sector caches.
Sector caches have the feature that large numbers of bytes can be tagged using relatively small numbers of tag bits, while still only transferring small blocks when a miss occurs. This suggests the use of sector caches for multilevel cache designs. In such a design, the cache tags can be placed at a higher level (e.g., on the processor chip) and the cache data array can be placed at a lower level (e.g., off-chip).
In this paper, we present a thorough analysis of the design and use of uniprocessor sector caches. We start by creating a standard workload and then we calculate miss ratios for a wide range of sector cache designs. Those miss ratios are transformed into Design Target Miss Ratios, which are intended to be "typical" miss ratios, suitable for use for design purposes ("design targets"). The miss ratios are then used to estimate performance, using typical timings, for a variety of one level and two level cache designs.
We find that for single level caches, sector caches are seldom advantageous. For multilevel cache designs with small amounts of storage at the first level caches, as would be the case for small on-chip caches, sector caches can yield significant performance improvements. For multilevel designs with large amounts of first level storage, sector caches provide relatively small improvements.
Sector Cache Design and Performance
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Electrical Engineering & Computer Sciences Technical Reports
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