As memory accesses increasingly limit the overall performance of reconfigurable accelerators, it is important for high-level synthesis (HLS) flows to adopt a systematic way to discover and exploit memory-level parallelism. This work develops 1) a framework where parallelism between memory accesses can be revealed from runtime profiles of applications and provided to a high level synthesis flow, and 2) a novel multiaccelerator/multi-cache architecture to support parallel memory accesses, taking advantage of the high aggregated memory bandwidth found in modern FPGA devices. Our experimental results have shown that for 10 accelerators generated from 9 benchmark applications, circuits using our proposed memory structure achieve on average 51% improved performance over accelerators using a traditional memory interface. We believe that our study represents a solid advance towards achieving memory-parallel embedded computing on hybrid CPU+FPGA platforms.
Title
Exploiting Memory-level Parallelism in Reconfigurable Accelerators
Published
2013-05-01
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2013-40
Type
Text
Extent
38 p
Archive
The Engineering Library
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