As integrated circuit manufacturing enters the nanometer regime, system performance variations are increasingly introduced through the growing complexity of the processing steps. Compact variability modeling has been widely studied for statistical circuit simulation to connect technology and design activities. Conventional statistical compact model parameter extraction methodology is not aware of the hybrid-hierarchical variation structure in the manufacturing processes. In this work we propose an efficient variability aware compact model characterization methodology based on variance linear propagation. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structure current/voltage measurements. In our implementation, spatial variability models of selected compact model parameters are created by linear regression on spatial pattern fitting coefficients with spatially modified sensitivity matrix. Good match is realized between our results and compact model parameter reference set obtained by full-wafer, direct model parameter extraction on a simple compact model and 65nm SOI industrial measurement data. Proper selection of both variability-aware model parameters and sensitive electrical measurements are also studied in this thesis work. Extensions on the proposed methodology can be applied to more complex compact models and more advanced hybrid-hierarchical variability models.





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