The proliferation of mobile electronic devices and the emergence of the Internet of Things (IoT) have brought energy consumption to the fore of challenges for future information processing devices. Digital logic integrated circuits (ICs) implemented with complementary metal-oxide-semiconductor (CMOS) transistors have a fundamental lower limit in energy efficiency because transistors are imperfect electronic switches, having non-zero OFF-state current (IOFF) and finite sub-threshold slope. In contrast, electro-mechanical switches (relays) can achieve zero IOFF and perfectly abrupt switching characteristics; therefore, they have attracted growing interest for ultra-low-power computing applications. A challenge for electro-mechanical relay technology is to reduce operation voltage and improve energy efficiency.

This dissertation addresses this challenge through relay design optimization for operation with an applied body bias voltage. The effects of body biasing on relay characteristics are systematically investigated by analytical modeling, simulation, and experiments. It is found that body biasing is an effective way to reduce the relay operation voltage, improve the energy-delay tradeoff, and ease fabrication challenges. By designing a logic relay to have relatively large structural stiffness and to operate in non-pull-in mode, less than 70 mV hysteresis voltage is experimentally demonstrated. A relay-based inverter circuit is demonstrated to operate reliably with a supply voltage below 100 mV, representing a significant milestone toward ultra-low-power mechanical computing.

This dissertation also includes an initial investigation of a more compact mechanical switch design for non-volatile memory application. The mechanical switch potentially can be used as a selector device in a cross-point memory cell array architecture, due to its zero off-state leakage current and non-linear current-vs.-voltage characteristics. Preliminary experimental results are shown and remaining challenges are discussed.