This paper presents an extension to the standard trace-driven simulation procedure that allows for the examination of parallel programs on parallel architectures. To demonstrate the procedure, an example simulation is performed to investigate the changes resulting from modifying the architecture of the Sequent multiprocessor. The trace-driven simulation process is shown to be a very lengthy task, and other methods of predicting performance are explored.
An Address Trace Generator for Trace-Driven Simulation of Shared Memory Multiprocessors
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