This report describes the internal organization of the SPUR floating point chip. The primary representation of the FPU microarchitecture is its functional level executable hardware description. This description serves as the primary chip design verification tool at both the functional and the layout levels. The text of this paper gives the operation sequence for the chip's instructions and details its datapath and control structures.
Functional Specification and Simulation of a Floating Point Co-Processor for SPUR
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Electrical Engineering & Computer Sciences Technical Reports
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