This report describes the internal organization of the SPUR floating point chip. The primary representation of the FPU microarchitecture is its functional level executable hardware description. This description serves as the primary chip design verification tool at both the functional and the layout levels. The text of this paper gives the operation sequence for the chip's instructions and details its datapath and control structures.
Title
Functional Specification and Simulation of a Floating Point Co-Processor for SPUR
Published
1986-08-01
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
CSD-87-311
Type
Text
Extent
62 p
Archive
The Engineering Library
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