In recent years, the explosive growth in data traffic has led to the demand for extremely high sample-rate ADCs. For example, high performance receivers for backplane channels and multi-mode fibers with DSP-based channel equalization or electronic dispersion compensation (EDC) rely on ADCs with sampling rates of greater than 10GS/s , . Similarly, emerging 100Gbps/400Gbps coherent fiber optics receivers with high degree of modulation require even higher sampling speed – greater than 50GS/s , . In these applications, moderate ENOB between 4 and 6 are required. In this report, the design techniques for building 6b 50GS/s ADC is presented. To demonstrate proposed circuits and design techniques, a 12.8GS/s 32-way hierarchically time-interleaved quarter ADC prototype is fabricated in 65nm CMOS. It achieved 4.6 ENOB and 25GHz 3dB effective resolution bandwidth (ERBW). As described in Section VII, the layout of the prototype is taken particular care so that it can be straight-forwardly expanded 51.2GS/s via additional interleaving without significantly impacting ERBW and FOM.